The archive · Hardware & Devices · Technical decision · 2022–2026
XCENA bets memory, not compute, is AI's bottleneck; $135M Series B at $570M
Samsung and SK Hynix veterans put thousands of RISC-V cores inside DRAM, betting AI inference is a memory problem; a $135M Series B at $570M follows.
XCENA
What the business is
XCENA designs MX1, a computational-memory controller that pairs up to 2TB of DRAM with thousands of small RISC-V cores and an in-house memory hierarchy, connecting to CPUs over CXL to handle AI inference's KV-cache and data-orchestration load inside the memory tier.
How it started
Jin Kim, Dohun Kim and Harry Juhyun Kim, veterans of Samsung and SK Hynix, the memory makers that supply Nvidia's GPUs, founded XCENA in 2022 on the observation that CPUs and GPUs got smarter every decade while memory stayed passive. Kim's framing: every ChatGPT request relays data between memory, CPU and GPU repeatedly, and that structural round-trip is the real cost driver of AI inference — so the company chose to make memory intelligent instead of racing to make GPUs bigger.
What happened
MX1 is still a prototype: a CXL-connected controller that bundles up to 2TB of DRAM with thousands of small RISC-V cores plus a homegrown memory hierarchy, interconnect bus and DRAM controller. XCENA says it can hold an LLM's KV cache and vector databases inside the memory tier, reuse KV caches across requests, and let one server do what used to take ten. In May 2026 the company closed a $135M Series B at a $570M valuation, roughly $185M raised in total, co-led by Seoul funds Atinum Investment and IMM Investment with Corstone Asia and earlier backers SBI Investment and Mirae Asset Capital. Kim told TechCrunch that talks with global memory vendors are at an early stage, that mass production on Samsung's 4nm process is scheduled by end-2026, and that revenue should start in 2027; the company has more than 90 staff across Pangyo and Sunnyvale and positions MX1 against Nasdaq-listed Astera Labs and Marvell, arguing its thousands of purpose-built cores beat their handful of general-purpose ones.
No ending yet — it is still running.
Background
XCENA is a Korea-US chip startup founded in 2022 by Jin Kim, Dohun Kim and Harry Juhyun Kim, veterans of Samsung and SK Hynix. Its product, MX1, is a computational-memory controller: up to 2TB of DRAM combined with thousands of small RISC-V cores, an in-house memory hierarchy, interconnect bus and DRAM controller, connected to CPUs over CXL. In May 2026 it raised a $135M Series B at a $570M valuation, bringing total funding to roughly $185M.
The founding bet is that AI inference has stopped being a pure compute problem and become a memory problem. Every ChatGPT request relays data between memory, CPU and GPU for every token generated, and MX1 is designed to handle that data orchestration — preprocessing, KV-cache management, caching — inside the memory module itself, so data no longer has to leave DRAM. CEO Jin Kim put it bluntly: 'CPUs and GPUs have both gotten smarter over the decades. Memory never did. XCENA wants to change that.'
Progress so far is engineering and capital, not revenue. MX1 is a prototype; XCENA says mass production on Samsung's 4nm foundry lines is scheduled for end-2026 with first revenue in 2027, and that talks with global memory vendors are early. The company claims one MX1-equipped server could do work that previously required ten, and its ideal customers are hyperscalers spending tens of billions a year on AI infrastructure. It has more than 90 staff split between Pangyo and Sunnyvale.
The bet is amplified by market timing: in May 2026 Samsung, SK Hynix and Micron each crossed a $1 trillion market cap as memory prices surged, which XCENA reads as a shift toward memory-centric AI infrastructure. The open risk is execution: shipping compute-in-memory at scale on Samsung's 4nm line, against Nasdaq-listed rivals Astera Labs and Marvell, before the memory wave crests.
What has to be true
- Every AI token still relays data between memory, CPU and GPU, so fixing the memory tier attacks a cost that scales with every request, not just model size.
- XCENA avoids fighting Nvidia on GPU math and instead owns the data-orchestration layer that still runs on CPUs inside the memory module.
- The May 2026 moment helped: memory prices and the three memory giants' trillion-dollar market caps made the memory-centric thesis feel current.
- Vertical integration — thousands of custom RISC-V cores plus its own interconnect and DRAM controller — gives an IP story against Astera Labs and Marvell.
- It is still a pre-revenue bet on an unproven chip, which is exactly what makes the $570M valuation a test of the thesis.
What can be applied
When everyone optimizes the same bottleneck, look at the layer they ignore: XCENA put compute inside DRAM, where incumbents left memory passive, and raised $135M at $570M before shipping.
Aftermath
As of 2026-09-02 XCENA is pre-revenue: MX1 remains a prototype, Samsung 4nm production is planned by end-2026, first revenue is targeted for 2027, and the $135M Series B (about $185M total raised) funds development, hiring and hyperscaler partnerships. It rides a market shift — Samsung, SK Hynix and Micron each crossed $1 trillion in market cap in May 2026 — and competes with CXL incumbents Astera Labs and Marvell. The open question is execution: whether its RISC-V cores deliver the promised ten-to-one server economics in production.
Sources
- This chip startup just raised $135M on a bet that AI's biggest bottleneck isn't compute — it's memory
- XCENA融资1.35亿美元开发计算内存控制器
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